Analysis of Potential Induced Degradation of Thin Film Solar Modules

Technology Trends

Over the last few decades, there have been numerous reports of degradation of PV modules caused by high voltage stress. This, in turn, generally affects the Energy Yield (EY) and the Return of Investment (RoI) of the PV installation.


This paper reviews briefly, findings from the past and reports on the effect of high voltage stress on thin film modules, in particular a-Si/µ-Si modules with TCO front side electrode. The experimental results also show that new modules are not always free of TCO corrosion and to secure the investment or/and make the PV installation bankable, it is important to prove the modules’ resistance against high voltage induced degradation.


To properly stress PV modules with high voltage and prove their resistance, it is important to understand the underlying degradation processes and to define the correct test sequence. UL has developed different test protocols to test c-Si [1], [2], [3] and thin film PV modules with respect to their susceptibility for high voltage degradation. This article will particularly address the case for thin film modules. Most thin film modules use a transparent conductive oxide (TCO) for the front side electrode. From observations in the past, this is one of the weak points of thin film modules, especially if not properly sealed against moisture ingress. In this article, we will focus on the moisture and high voltage induced degradation mode, which could potentially be a dominating failure mode, given India’s tropical climatic conditions.


Remark: Marketing the statement and the promise that modules from a Brand are PID or TCO corrosion resistant is good, but not enough. Using results from recently installed a-Si/µ-Si modules, this article will reveal that the problem of TCO is still present. UL provides several bankability and quality services to address the different degradation modes and together with the client and the knowledge of the installation site, a well-defined test procedure can be determined and executed swiftly within our laboratories in India or around the world.



Module qualification tests such as IEC 61215 [4] and IEC 61646 [5] for c-Si and thin-film modules respectively, have shortcomings in their ability to evaluate some degradation mechanisms that modules could experience. A test to measure a module’s ability to withstand a continuous system voltage bias is not included in the present module qualification standard as it was deemed too stressful several years ago [7]. This unfortunate omission has significantly cost the industry in terms of effort and expenditure. Based on the numerous published and unpublished reports of PV module degradation, several modes can be identified which are dependent on location and module technology [8], [9], [10]. Each solar cell technology shows its own behavior with respect to high system voltages in PV power plant arrays [7], [11], [12]. Additionally, the trend towards higher system voltages (à 1500V) is increasing the voltage induced stress to all PV components,


It has been found that most PV-cell technologies are only prone to system voltage stress in one polarity. Proper grounding is a possibility to avoid a degradation phenomenon. But the PV inverter development trend is moving towards transformerless setups, due to cost reductions and efficiency gains. This will eventually lead to the need to test PV- technologies in the future to both polarities, to ensure no or low system potential induced degradation rates. Besides hard grounding, there are other possibilities to prevent or slow down PID. These are outlined and discussed in figure [2], [3].

The following gives a brief summary on how the high voltage qualification tests have evolved over time.

Over the past years, several test setups have been developed for the different PV module technologies. The main difference is the application of the high potential to the cells, where typically two approaches are used.


By humidity in a climatic chamber (biased Damp-heat (DH))

By conductive foil, typically Al-foil

Both these setups have advantages and disadvantages. For p-type crystalline Silicon technologies, the following conditions are mainly used:


Bias DH: 60°C or 85°C / 85 %, -Usyst (typically -1000V)

25°C (room temperature (RT)), Al-foil front contact, -Usyst (typically -1000V)

These test conditions are included in the most recent IEC 62804 draft (summer 2014) [6]. As mentioned, these parameters focus mainly on crystalline modules. But several learnings can be gathered from the achievements of crystalline Silicon module testing. As recently published [11], it is important to control humidity and the start of the high voltage stress very carefully to achieve reproducible results. This is independent of the solar cell technology and also applies to thin film module PID tests. Together with the results published in [7], this can be used as a guide on how to test thin film modules with respect to their susceptibility against high voltage stress.


To choose the right test, it is important to know and understand the underlying degradation mode. If for example, moisture is needed to trigger a reaction, as it is for TCO corrosion, only the first method can be applied. For Sodium ion migration due to electric fields, both methods can be used, but will result in different stress levels due to different homogeneity of the applied potential. UL favors method 2) in these cases, with the conductive foil front side electrode to ensure worst case testing, as it represents rain or dew/moisture condensation events in the field during day time.



In the past, a lot of thin film companies either stated that they did not have problems with respect to high voltage stress or released new installations instructions to allow for transformer less inverters, which means that the strings are on a floating potential and the modules on at least one side of the module string will be exposed to a hazardous high potential. Not all modules are well protected as shown in the example on the left side in Figure 1. The so called “bar-graph” TCO corrosion can be easily seen.


To investigate today’s modules, UL performed tests on a-Si/µ-Si Tandem junction thin film modules to demonstrate that the failure can easily be reproduced in the laboratory and that some of today’s modules are still sensitive to this kind of non-reversible high voltage induced degradation. The results are shown and discussed in the next secion.




Figure 1: left: image from module out of the field that shows TCO (bar-graph) corrosion and right: corrosion of front electrode (TCO) due to accelerated aging (PID) test in the lab for 100hours.



This section will display the experimental results from thin film a-Si/µ-Si modules achieved by a series of tests to look into the output power trend, occurrence of shunts and safety in terms of protection against electric shock.



In the past, most tests were performed on new, out-of-the-box PV modules. In some rare cases, studies were done on modules taken out of an existing installation as is the case with this study. The main objective is to demonstrate on non-effected modules, that all modules of this type are susceptible to the observed visual defects (similar to those shown in Figure 1 on the left side). This kind of test has the advantage of a one-by-one comparison. The obtained results show the relevance of that kind of testing and the obvious similarities of the outcome.

Due to the fact that the modules were not new, some aspects had to be checked in advance to get a better understanding of the status of the modules. The following steps were taken:


Initial characterization

Light soaking (to see if the modules are in a stabilized state), including characterization

PID testing in several steps with intermediate characterization.

Each characterization step usually included a Flash test for performance verification, Electroluminescence (EL) images and insulation resistance tests for safety verification.

Light soaking was performed in accordance with IEC 61646 [5] and PID testing was done in a standard damp heat chamber with a temperature setting of 85°C and a relative humidity of 85%. Voltage stress level was set to system voltage (-1000V). Within the PID test steps, the module’s output power was measured without any stabilization steps.






This section will show the experimental results based on the individual characterization techniques.


Before and after each test step, the modules were visually inspected. Besides some bubble formation and light glass corrosion, the modules started to show severe TCO corrosion (see Figure 1 right image). This accurately reproduced the findings out of the field and proved the approach to look into TCO corrosion with a damp heat experiment, with an applied high potential between modules active circuitry and the surrounding climate chamber.



The image shown in Figure 1 was observed after just 100hours of testing. Further testing increased the affected area.

Flash testing – Module performance

The Flash testing results are shown in Figure 2 as a function of PID test time. First an increase in output power is observed and after approx. 200hours the power started to degrade for modules 1 and 3. Module 2 shows a somewhat different behavior. This will be discussed and explained later.

Here it is important to understand that the modules were in a light soaked/stabilized stage in the beginning of the experiment (0 hours).Then two competing effects occurred:



TCO corrosion (see Figure 1

Stabler Wronski effect.

The second effect will occur at elevated temperatures (typically above 60°C with a significant rate) and will lead to an increase in output power in the beginning of the experiment in the range of 15-25% dependent on solar cell junction design. The TCO corrosion will lead to a power reduction, proportional to the affected area. This is the dominant factor for longer test durations.




Figure 2: Module’s power output during the PID test.



EL images were taken to look into the homogeneity of the module. Bright areas represent active areas with an intact solar cell whereas dark areas ether represent non-active regions like contact scribing, shunts (darks spots) or corroded/degraded/damages absorber areas.


Figure 3 shows exemplarily, the same module before and after 100hours of PID testing with obvious findings visible.



Top: Dark area around module’s junction box significantly increased

Edges of the module got generally darker

The number of larger dark spots increased significantly.

Note: the tiny dark spots in the left images are not visible due to contrast adjustments.




Figure 3: Electroluminescence images: left: before PID test (0hours) and right after 100hours of PID test.





The insulation resistance of the module was investigated with a dry-high-pot and a wet-leakage current test.


Figure 4 plots the trend of the wet-leakage resistance as a function of the experimental step. In the first step (light soaking), the modules slightly dry-out and then on resistance, slightly increases. After the first 50hours of damp heat penetration, the highest reduction of resistance is visible but the trend towards lower values continues. IEC 61646 [5] sets, for this kind of module, a lower limit of 40Mohm*m² (for the used modules the lower limit is ~30MOhm). From a normative point of view, the modules still pass the test. But a reduction of a factor of 3 is significant and points towards problems with the edge insulation system that might be caused by bad material, problems in production processes or/and module handling.




Figure 4: Wet-leakage resistance measured before and after the individual Damp-heat/PID of three equivalent samples.



While the modules in the insulation resistance display similar behavior, they show a different trend in power loss during the PID test. One module started to degrade much earlier and also did not show the same power increase due to the annealing (high temperature state of a-Si material à Stabler-Wronski effect) caused by the 85°C during the damp-heat PID test.

To better understand this behavior, the corroded area of each module was measured and plotted for each sample, (Figure 5) after 400hours of PID-test. The left axis represents the corroded area in arbitrary units and the right axis (crosses with line) the measured power loss with respect to the start of the PID test (0hours).

Sample #2 that displayed the slightly odd behavior showed much more TCO corrosion and therefore lost much more active area. The higher corrosion rate quickly compensated the power increase due to the Stabler-Wronski effect.



It is therefore concluded that it is very helpful to collect different data points at different stages of the test. Here the combination of visual inspection and Flash-test helped to better understand the power degradation of the module. The collected EL images gave additional insight due to their higher spatial resolution and the possibility to make shunts visible. The darkened area in the EL images also correlated well with the visually observed TCO corrosion.





Figure 5: Powerloss (red) and corroded area (blue) after 400hours of damp heat PID test at -1000V.



This article is a reminder of the importance of high quality project due diligence. This includes the verification of module quality shipped and installed at a specific location. Depending on known failure modules of a certain solar cell technology and the installation location’s weather, a suitable test protocol should be defined and executed. Root cause failure analysis and finally the replacement of thousands of modules is much more costly compared to upfront testing.

Based on years of testing and research expertise, UL is equipped to define the protocols for quality assurance. Additionally, advice for root cause failure analysis can be given and tests for the analysis can be performed within UL’s laboratories in India and around the globe.

PID is still a major problem in today’s PV modules, nearly independent of the technology. Both c-Si and thin film modules, can exhibit dramatic power losses due to high voltage stress.


   [1]    [1] B. Jaeckel et al, “PV Module degradation under high potentials – A comparative study between test setups”, 28th European Photovoltaic Solar Energy Conference, 2013


[2] B. Jaeckel et al., “Investigation of c-Si Modules Degradation and Recovery Effect under High Potentials: CV-PID”, 40th IEEE Photovoltaic Specialists Conference, 2014


[3] B. Jaeckel et al, “Investigation of c-Si modules degradation and recovery effect under high potentials”, 30th European Photovoltaic Solar Energy Conference, 2014


[4] IEC 61215 Ed. 2 - Crystalline silicon terrestrial photovoltaic (PV) modules- design qualification and Type approval.


[5] IEC 61646 Ed. 2 – Thin-Film terrestrial photovoltaic (PV) modules – Design qualification and type approval. Edition 2.0 2008-05


[6] IEC 62804 Ed. 1 draft - System voltage durability test for crystalline silicon modules design qualification and type approval.


[7] P. Lechner et al, “Estimation of Time to PID-failure by Characterization of Module Leakage Currents”, 27th European Photovoltaic Solar Energy Conference, 2012


[8] S. Koch et al, “Polarization Effects and Tests for Crystalline Silicon Cells”, 26th EUPVSEC. Hamburg. Germany. 2011.


[9] J. Berghold et al, “PID test round robins and outdoor correlation”, 28th European Photovoltaic Solar Energy Conference, 2013


[10] C.R. Osterwald et al, “History of accelerated and qualification testing of terrestrial photovoltaic modules: A literature review,” Prog. Photovolt: Res. Appl. 17 (2009) pp. 11–33.


By N. Srimathy, B. Jaeckel, R. Prathap UL (Underwriters Laboratories)